? 1 ? CXG7002FN 26 pin hsof (plastic) power amplifier/antenna switch + low noise amplifier/down conversion mixer for phs notes on handling gaas mmics are esd sensitive devices. special handling precautions are required. description the CXG7002FN is an mmic consisting of the power amplifier, antenna switch, low noise amplifier and down conversion mixer. this ic is designed using the sony?s gaas j-fet process featuring a single positive power supply operation. features ? operates at a single positive power supply: v dd = 3v small mold package: 26-pin hsof low current consumption: i dd = 150ma (p out = 20.2dbm, f = 1.9ghz) high power gain: gp = 39db typ. (p out = 20.2dbm, f = 1.9ghz) low current consumption: i dd = 2.5ma typ. (when no signal) low noise: nf = 2.7ma typ. (f = 1.9ghz) high conversion gain: gc = 9db typ. (f = 1.9ghz) low distortion: input ip3 = +1dbm typ. (f = 1.9ghz) applications digital cordless telephones (phs) structure gaas j-fet mmic absolute maximum ratings supply voltage v dd 6v voltage between gate and source v gso 1.5 v gain control voltage vp ctl 2.5 v drain current i dd 550 ma allowable power dissipation p d 3w control voltage v ctl 6v supply voltage v dd 6v input power p rf +10 dbm channel temperature tch 150 c operating temperature topr ?35 to +85 c storage temperature tstg ?65 to +150 c recommended operating conditions supply voltage v dd 2.7 to 3.3 v gain control voltage vp ctl to v dd ? 1.0 v control voltage (h) v ctl (h) 2.9 to 3.3 v control voltage (l) v ctl (l) 0 to 0.2 v e04738-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits.
? 2 ? CXG7002FN block diagram and external circuit pin configuration 2.2nh p in 18nh 1nf 1nf v dd 1 18nh 1nf 30pf v dd 2 56nh 1nf 8pf 100pf 1.8nh 10nf v dd 3 v ctl 2 100pf 1k (v gg 1) (p out ) (t x ) vp ctl 1pf 100pf v gg 2 if out 30pf 100nf 1nf 3.9nh 2.7nh (rf in ) (r x ) ant rf in (mix) v dd (lo amp) lo in v ctl 1 30pf 30pf 100pf 2.2nh rf out v dd (rf amp) 3.9nh 1.5nh 1nf 1nf 18pf 100pf 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 20 22 23 24 25 26 v dd (if amp) v gg 1 vp ctl v gg 2 p out t x v ctl 1 ant gnd rf out /v dd (rf amp) gnd rf in (mix) v dd (lo amp) lo in p in gnd v dd 1 v dd 2 v dd 3 gnd r x v ctl 2 rf in cap gnd cap if out /v dd (if amp) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 20 22 23 24 25 26
? 3 ? CXG7002FN pin description pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 symbol loin v dd (lo amp) rf in (mix) gnd rf out /v dd (rf amp) gnd ant v ctl 1 tx p out v gg 2 vp ctl v gg 1 p in gnd v dd 1 v dd 2 v dd 3 gnd rx v ctl 2 rf in cap gnd cap if out /v dd (if amp) description local signal input pin v dd pin of local amplifier rf (mix) signal input pin gnd pin rf amplifier output and v dd pin gnd pin antenna switch pin this pin is ant-tx or ant-rx by setting of v ctl 1 and v ctl 2. antenna switch control pin 1 tx pin signal is input to antenna switch during ant-tx. power amplifier output pin gate voltage adjustment pin of power amplifier (rear-end fet) 2 gain control pin of power amplifier (first stage fet) gate voltage adjustment pin of power amplifier (first stage, middle stage fet) 1 signal input pin to power amplifier gnd pin v dd 1 pin of power amplifier (first stage fet) v dd 2 pin of power amplifier (middle stage fet) v dd 3 pin of power amplifier (rear-end fet) gnd pin rx pin ant input signal is output to this pin during ant-rx. antenna switch control pin 2 rf signal input pin external capacitor connection pin this pin is connected to lna fet source. rf amplifier characteristic is optimized during 1.9ghz by this capacitor (typ. 1nf). gnd pin external capacitor connection pin if amplifier distortion is improved by this capacitor. if output and if amplifier v dd pin
? 4 ? CXG7002FN electrical characteristics 1. control pin logic for antenna switch conditions of control pins v ctl 1 = 3v, v ctl 2 = 0v v ctl 1 = 0v, v ctl 2 = 3v ant-t x on off ant-r x off on 2. power amplifier block + antenna switch transmitter block these specifications are when the sony's recommended evaluation board with the external circuit shown on page 8 is used. therefore, the power amplifier output pin (p out ) and the antenna switch transmission input pin (tx) are connected via an external circuit. the specifications of the power amplifier block are set including the antenna switch transmitter block. unless otherwise specified: v dd = 3v, vp ctl = 2v, v ctl 1 = 3v, v ctl 2 = 0v, i dd = 150ma, p out = 20.2dbm, f = 1.9ghz, ta = 25c unit item current consumption gate voltage adjustment value output power power gain adjacent channel leak power ratio (600 100khz) adjacent channel leak power ratio (900 100khz) occupied bandwidth 2nd-order harmonic level 3rd-order harmonic level measured with the ant pin measured with the ant pin measured with the ant pin measured with the ant pin measured with the ant pin measured with the ant pin measurement conditions ma v dbm db dbc dbc khz dbc dbc symbol i dd v gg p out g p acpr600khz acpr900khz obw ? ? max. 0.6 ?55 ?60 275 ?25 ?25 ty p. 150 0.25 39 ?63 ?70 250 min. 0 20.2 36
? 5 ? CXG7002FN 3. antenna switch receiver block + font-end block these specifications are when the sony's recommended evaluation board with the external circuit shown on page 8 is used. therefore, the antenna switch reception pin (rx) and the low noise amplifier input pin (rf in_lna ) are connected via an external circuit. the specifications of the low noise amplifier block are set including the antenna switch reception block. (a) antenna switch receiver block + low noise amplifier block unless otherwise specified: v dd = 3v, v ctl 1 = 0v, v ctl 2 = 3v, rf = 1.9ghz/?30dbm, ta = 25c unit max. 3.5 16.5 3.5 ty p. 2.5 14.5 2.7 ?8 30 min. 12.5 ?11 25 item current consumption power gain noise figure input ip3 isolation when no signal ? 1 measurement conditions ma db db dbm db symbol i dd_lna g p nf iip3 i so ? 1 conversion from im3 compression r atio during rf1 = 1.9000ghz/?30dbm and rf2 = 1.9006ghz/?30dbm input. unit max. 2.5 4.5 11 11.5 ?38 ty p. 1.7 3.3 9 8.5 +1 ?43 min. 7 ?2 item lo block current consumption if block current consumption conversion gain noise figure input ip3 lo to ant leak when no signal when no signal ? 2 ? 3 measurement conditions ma ma db db dbm dbm symbol i dd_lo i dd_if g c nf iip3 plk ? 2 conversion from im3 compression ratio during rf1 = 1.9000ghz/?25dbm and rf2 = 1.9006ghz/?25dbm input. ? 3 the rf out pin of the lna and the rf in pin of the mix block is connected directly with the cable. and the power supply of the lna is turned on. (b) mixer block unless otherwise specified: v dd = 3v, rf = 1.90ghz/?25dbm, lo = 1.66ghz/?12dbm, ta = 25c unit max. 10 ty p. 7.5 min. item current consumption when no signal measurement conditions ma symbol i dd_ total (c) total of (a) + (b)
? 6 ? CXG7002FN example of representative characteristics 1. power amplifier + antenna switch transmitter block (f = 1.9ghz, ta = 25c) p out , acpr600khz vs. p in p in ? input power [dbm] p out ? output power [dbm] acpr600khz ? adjacent channel leak power ratio [dbc] ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?5 0 5 10 15 20 25 gp, acpr600khz vs. vp ctl vp ctl ? gain control voltage [v] gp ? power gain [db] acpr600khz ? adjacent channel leak power ratio [dbc] 0 0.5 1.0 1.5 2.0 2.5 3.0 ?70 ?65 ?60 ?55 ?50 ?45 ?40 15 20 25 30 35 40 gp 45 acpr600khz acpr600khz v dd = 3v, vp ctl = 2v, v gg = const., v tcl 1 = 3v, v ctl 2 = 0v i dd = 150ma (@p out = 20.2dbm), p in = var. p out , acpr600khz vs. v dd v dd ? supply voltage [v] p out ? output power [dbm] acpr600khz ? adjacent channel leak power ratio [dbc] 2.0 2.5 3.0 3.5 4.0 4.5 5.0 ?70 ?65 ?60 ?55 ?50 ?45 ?40 17 18 19 20 21 22 23 v dd = var., vp ctl = 2v, v gg = const., v tcl 1 = 3v, v ctl 2 = 0v i dd = 150ma (@v dd = 3v, p out = 20.2dbm), p in = ?19.2dbm v dd = 3v, vp ctl = var., v gg = const., v tcl 1 = 3v, v ctl 2 = 0v i dd = 150ma (@vp ctl = 2v), p in = var., p out = 20.2dbm p out acpr600khz gp, acpr600khz vs. i dd i dd ? current consumption [ma] gp ? power gain [db] acpr600khz ? adjacent channel leak power ratio [dbc] 100 120 140 160 180 200 220 ?70 ?65 ?60 ?55 ?50 ?45 ?40 36 37 38 39 40 41 42 v dd = 3v, vp ctl = 2v, v gg = var., v tcl 1 = 3v, v ctl 2 = 0v i dd = var., p in = var., p out = 20.2dbm gp acpr600khz p out
? 7 ? CXG7002FN 2. antenna switch receiver block + low noise amplifier, down conversion mixer (ta = 25c) sw/lna block: p out , p im3 vs. p in p in ? rf input power [dbm] p out ? rf output power, p im3 ? 3rd-order intermodulation power [dbm] p out ? if output power, p im3 ? 3rd-order intermodulation power [dbm] ?50 ?40 ?30 ?20 ?10 0 ?100 ?80 ?60 ?40 ?20 p out p im3 0 20 v dd = 3v, rf1 = 1.9000ghz, rf2 = 1.9006ghz v ctl 1 = 0v, v ctl 2 = 3v mix block: p out , p im3 vs. p in p in ? rf input power [dbm] ?40 ?30 ?20 ?10 0 10 ?100 ?80 ?60 ?40 ?20 0 20 v dd = 3v, rf1 = 1.9000ghz, rf2 = 1.9006ghz lo = 1.66ghz/?12dbm mix block: input ip3, p lk vs. p lo p lo ? lo input power [dbm] input ip3 [dbm] ?25 ?20 ?15 ?10 ?5 0 ?1.0 ?0.5 0 0.5 1.0 1.5 p lk 2.0 p lk ? lo to ant leak level [dbm] ?55 ?50 ?45 ?40 ?35 ?30 ?25 v dd = 3v, rf = 1.90ghz/?25dbm, lo = 1.66ghz v ctl 1 = 0v, v ctl 2 = 3v lna output pin and mix input pin is directly connected with the cable. mix block: gc, nf vs. p lo p lo ? lo input power [dbm] gc ? conversion gain [db] ?25 ?20 ?15 ?10 ?5 0 7.0 7.5 8.0 8.5 9.0 9.5 gc 10.0 nf ? noise figure [db] 6 7 8 9 10 nf 11 12 v dd = 3v, rf = 1.90ghz/small signal, lo = 1.66ghz input ip3 p out p im3 input ip3 input ip3
? 8 ? CXG7002FN recommended evaluation board enlarged diagram of external circuit block glass fabric-base epoxy board (4 layers) thinkness between layers 1 and 2: 0.2mm dimensions: 50mm 50mm via hole via hole vp ctl v dd_lo v dd_if v ctl 2 v gg ant rf in_mix rf out_lna if out pa in lo in v dd_pa CXG7002FN v dd (pa) v ctl 2 v ctl 1 vp ctl v gg v dd (if) v dd (lo) v dd (lna) c6 c6 c8 c2 c6 c6 c6 c5 c5 c5 c5 r1 c1 c4 c4 l3 l3 l5 l1 c3 c6 c6 c4 c4 c7 c5 l2 l5 l4 l7 l6 l6 r1 = 1k l1 = 1.5nh l2 = 1.8nh l3 = 2.2nh l4 = 2.7nh l5 = 3.9nh l6 = 18nh l7 = 56nh c1 = 1pf c2 = 8pf c3 = 18pf c4 = 30pf c5 = 100pf c6 = 1nf c7 = 10nf c8 = 100nf
? 9 ? CXG7002FN sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating copper alloy package structure 0.06g hsof-26p-01 hsof 26pin (plastic) b 0.4 3.8 0.05 4.4 0.1 0.07 m ? 5.6 0.05 1 13 14 26 a s a s 0.9 0.1 0.08 s (1.5) (0.7) 0.5 0.2 4.4 0.2 4.2 5.5 0.4 (1.75) 0.45 0.15 note: dimension ? ? ? does not include mold protrusion. 0.14 ? 0.03 detail b 0.2 0 + 0.05 (0.2) 0.2 0.05 solder plating + 0.05 lead plating specifications item lead material copper alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18m spec. sony corporation package outline unit: mm
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